digital multiplier
英 [ˈdɪdʒɪtl ˈmʌltɪplaɪə(r)]
美 [ˈdɪdʒɪtl ˈmʌltɪplaɪər]
数字乘法器
双语例句
- The Design of CMOS Digital Multiplier with Concurrent Structure
具有并发结构的CMOS数字乘法器设计 - DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
数字信号处理（DSP）具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。 - In this paper, a new optimization method based on Immune Memory Clonal Selection Algorithm ( IMCSA) for designing digital filters with coefficients in sum of power of two ( SOPOT), which can be implemented without multiplier, is proposed.
文章提出了一种基于免疫记忆克隆选择算法设计整型数字滤波器的方法，可获得频率特性很好的数字滤波器，克服量化系数引起的滤波器性能降低问题，而且可降低滤波器实现的复杂度。 - A Wholly Digital Frequency Multiplier of Low Frequency and High Precision
一种低频高精度全数字化倍频器 - A monolithic 16 × 16 digital multiplier
一个单片16×16位乘法器 - DSP adopts Harvard structure in which program memory and data memory are divided. DSP can realize various digital signal process algorithms by special hardware multiplier.
DSP内部采用程序和数据分开的哈佛结构，具有专门的硬件乘法器，可以用来快速地实现各种数字信号处理算法。 - Design of a Digital Multiplier Based on an 8-Bit RISC Microcomputer
一种基于RISC结构单片机的数字乘法器的设计 - Development of a Digital Dynamometer Based on Time-Divided Multiplier
基于时分割乘法器的数字功率表的研制 - Design of Digital Multiplier Based on FPGA
基于FPGA数字乘法器的设计 - The design of on-line harmonics analysis instrument based on the digital analog mixed multiplier
基于数字模拟混合乘法器的谐波在线分析仪设计 - The Study of Middle Sampling Analog Digital Mixed Multiplier
中点采样模拟数字混合乘法器的研究 - A new type programmable self-adaptive digital frequency multiplier
一种新型的可编程自适应数字频率倍频器 - Practice shows that it is a practical digital multiplier.
实践表明，这是一种实用的数字乘法器。 - A new pulse stream digital/ analogue based synapse multiplier/ adder can be realized. The synapse weight values don't need learning, and it can also lessen the complexity of circuit.
实现了一种脉冲流数字模拟混合突触乘法/加法器电路，而且该神经网络电路的突触权值不需要学习调整，降低了电路的复杂性。 - Hardware realization of60 channel TMUX digital signal processor by using of RALU and multiplier is proposed in this paper.
本文提出采用乘法器和RALU实现60路复用转换器主处理器硬件的方案。 - A Digital Multiplier for Video Processing
一种图像处理用的数字乘法器 - Introduces a new type programmable self-adaptive digital frequency multiplier. Comparing with traditional analog and digital frequency multipliers, it has the advantages of high tracking speed, high phase accuracy, and wide frequency range.
介绍了一种新型可编程自适应数字频率倍频器，与传统的模拟和数字倍频器相比，它具有跟踪速度快、相位精度高和频率范围宽等优点。 - Compensation and Error Analysis of Digital Frequency Multiplier for Spectrum Analysis of Periodic Signals
数字倍频器用于周期信号频谱分析的补偿和误差分析 - The paper proposed a signal equal divided middle sampling analog digital multiplier.
本文提出了一种信号等区间分割、中点采样模拟数字混合乘法器。 - A single-level perceptron network and field effect transistor circuit were used to make a digital/ analogue-based synapse multiplier/ adder.
利用单层感知器网络、场效应管电路实现了一种新的数字模拟混合突触乘法/加法器电路。 - A Design of Digital Phase& locked Frequency Multiplier
全数字化锁相倍频器的设计 - The chapter 4 discuss some question of the circuit using programmable device like digital phase locked loop and digital frequency multiplier, it can increase the way of circuit design.
第四章探讨了运用可编程技术设计数字锁相环和数字倍频器的相关问题，为以后电路设计拓展更多的方法。 - Design of IP core: transfer the algorithm model into IP modules. ( 1) The whole IP core is combined of three functional modules, digital LPF, amplitude/ phase solution module and signed multiplier module.
IP模块设计：将已通过仿真的算法模型，转换成IP模块。（1）整个IP模块分成三个功能模块&数字低通滤波模块、幅度/相位求解模块和有符号小数乘法模块。 - High performance multiplier is the important component of the digital signal processor, the key to implement the signal processing and image processing; Multiplier always has large area, long latency and complex structure.
高性能乘法器是现代数字信号处理器（DSP）中的重要部件，是完成高性能实时数字信号处理和图像处理的关键所在。浮点乘法器具有面积大、延迟长、结构复杂的特点。 - Secondly, put forward a new kind of digital serial pulse structure, based on the structure designed series-parallel mixed modular multiplier, which achieved best matching on both speed and area.
其次，提出了一种新型数字串行脉冲阵列结构，设计了基于此结构的串并混合模乘器，在速度和面积上达到了最佳匹配。 - In order to achieve high integration and reduce chip resources share, the CORDIC algorithm was used to implement programmable digital down converter module which reduced the use of multiplier and look-up table.
为了达到高集成度，减少芯片资源占有率，本文采用了CORDIC算法实现可编程下变频模块，减少了乘法器和查找表的使用。 - Multiplier is an important component of microprocessor, and directly affects the performance of the whole digital system. For this reason, study on design of high-performance multiplier is still concerned.
乘法器是微处理器中的重要部件，它的设计与实现直接影响着整个数字系统的性能，因此高性能乘法器的设计仍然被关注。 - As an important component of digital signal processor, the speed of multiplier determines the performance of it directly.
乘法器作为数字信号处理器的重要部件，它的速度直接决定了整个处理器的性能。 - A kind of NCO structure for digital down conversion based on the combination of multiplier and looking-table is implemented which uses less multipliers and memory, thus can save a lot of resources of FPGA.
研究了数字下变频中NCO的原理，使用了一种乘法器和查表相结合的NCO实现方法，该结构只使用较少的乘法器和存储器，占用FPGA资源较少。 - Realize synchronous sampling of steady state current by the digital frequency multiplier programmed with VHDL language on FPGA. The digital frequency multiplier was simulated, measured, and the results were analyzed in detail.
采用基于FPGA的数字倍频实现稳态电流同步采样，文中详细阐述了数字倍频原理及实现。采用VHDL语言编程并仿真、实测，对实验结果进行了详实的对比分析。